soft and program: comp.programming.threads - 5 new messages in 3 topics

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Today's topics:

* Call for Papers: The 2009 International Conference on e-Learning, e-Business,
Enterprise Information Systems, and e-Government (EEE'09), USA, July 13-16,
2009 - 1 messages, 1 author
http://groups.google.com/group/comp.programming.threads/t/38f8a3c82d9d4c31?hl=en
* what is memory addressing ? - 3 messages, 3 authors
http://groups.google.com/group/comp.programming.threads/t/12c59a69cdbcf172?hl=en
* Call for Papers: The 2009 International Conference on Parallel and
Distributed Processing Techniques and Applications (PDPTA'09), USA, July 13-16,
2009 - 1 messages, 1 author
http://groups.google.com/group/comp.programming.threads/t/7e024923f4068687?hl=en

==============================================================================
TOPIC: Call for Papers: The 2009 International Conference on e-Learning, e-
Business, Enterprise Information Systems, and e-Government (EEE'09), USA, July
13-16, 2009
http://groups.google.com/group/comp.programming.threads/t/38f8a3c82d9d4c31?hl=en
==============================================================================

== 1 of 1 ==
Date: Fri, Nov 28 2008 10:20 pm
From: "A. M. G. Solo"

C A L L F O R P A P E R S
===============================

CALL FOR PAPERS
and
Call For Workshop/Session Proposals

The 2009 International Conference on e-Learning,
e-Business, Enterprise Information Systems,
and e-Government
EEE'09

Date and Location: July 13-16, 2009, Las Vegas, USA

You are invited to submit a paper (and/or a proposal to organize
a session/workshop). All accepted papers will be published in the
respective conference proceedings.

SCOPE: Topics of interest include, but are not limited to, the
following:

O e-Learning:
- e-Learning design and methodologies
- e-Learning technologies and tools
- Authoring tools
- e-Learning portals
- Instructional design methodologies
- Social impact and cultural issues in e-Learning
- Content management and development
- Policy issues in e-Learning
- On-demand e-Learning
- e-Learning standards
- Assessment methodologies
- Knowledge management
- Virtual learning environments
- Audio and video technologies for e-Learning
- Usability issues
- AI and e-Learning
- On-line education (all levels: elementary, secondary, ...)
- Open-source e-Learning platforms
- Training and evaluation strategies
- e-Universities
- Case studies and emerging applications

O e-Business:
- e-Business systems integration and standardization
- Electronic negotiation systems and protocols
- Internet payment systems
- e-Retailing and web design
- e-Procurement methods
- Techniques for B2B e-Commerce
- Global e-Commerce and e-Business
- Service-oriented e-Commerce
- Trust, security, and privacy in e-Commerce and e-Business
- Intelligence in e-Commerce
- Databases and e-Commerce applications
- Business-oriented and consumer-oriented e-Commerce
- Development of e-Business and applications
- e-Business in developing countries
- Marketing on the web
- Organizational and management issues
- Supply chain management
- e-Business models and architectures
- Applications of new technologies to e-Business
- Middleware technologies to support e-business
- Case studies and applications

O Enterprise Information Systems:
- Enterprise resource planning and e-Business
- Strategic decision support systems
- Organizational semiotics and semiotics in computing
- Data warehouses and technologies
- middleware integration
- Intranet and extranet business applications
- Databases and information systems integration
- Intelligent agents
- Enterprise-wide client-server architectures
- Knowledge management
- Information systems analysis and specification
- Ontology engineering
- CASE tools for system development
- B2B and B2C applications
- Business processes re-engineering
- Market-spaces: market portals, hubs, auctions, ...
- Semantic web technologies
- Web interfaces and usability
- Human factors and e-Learning
- Case studies and applications

O e-Government:
- Legal aspects of e-Government
- Risk management
- Methods and tools for e-Government
- Policies and strategies
- Designing web services for e-Government
- e-Democracy and e-Voting
- Trust and security in e-Government
- Enterprise architecture for e-Government
- Interoperability frameworks in e-Government
- Inter-administration and G2G issues
- Public and private partnership
- Teaching e-Government
- Case studies

Web links:
http://www.world-academy-of-science.org/worldcomp09/ws/conferences/eee09
http://www.world-academy-of-science.org/

ACADEMIC CO-SPONSORS:

Currently being prepared - it will include a number of active
research laboratories and centers that have helped to shape our
field. The Academic Co-Sponsors of the last offering of
EEE included research labs at Harvard University, UCLA,
University of Minnesota, University of Illinois at Urbana-
Champaign, Georgia Institute of Technology, Emory University,
University of Texas at Austin, MIT, George Mason University,
University of Iowa, Russian Academy of Sciences, NEMO/European
Union, and others. Corporate Co-Sponsors included, Google,
Salford Systems, Synplicity, Supermicro, NIIT, and others.

General Co-Chair and Coordinator:

H. R. Arabnia, PhD
Professor, Computer Science
Editor-in-Chief, The Journal of Supercomputing (Springer)
Advisory Board, IEEE Technical Committee on TCSC
Vice President, Int'l Society of Intelligent Biological Medicine
The University of Georgia
Department of Computer Science
415 Boyd Building
Athens, Georgia 30602-7404, USA

Tel: (706) 542-3480
Fax: (706) 542-2966
E-mail: hra@cs.uga.edu

SUBMISSION OF PAPERS:

Prospective authors are invited to submit their draft papers by
uploading them to http://worldcomp.cviog.uga.edu/ .
Submissions must be received by Feb. 25, 2009 and they must be in
either MS doc or pdf formats (about 5 to 7 pages - single space,
font size of 10 to 12). All reasonable typesetting formats are
acceptable (later, the authors of accepted papers will be asked to
follow a particular typesetting format to prepare their papers for
publication.)

The length of the Camera-Ready papers (if accepted) will be limited
to 7 (IEEE style) pages. Papers must not have been previously
published or currently submitted for publication elsewhere. The
first page of the draft paper should include: title of the paper,
name, affiliation, postal address, and email address for each
author.
The first page should also identify the name of the Contact Author
and a maximum of 5 topical keywords that would best represent the
content of the paper. Finally, the name of the conference (EEE)
must be mentioned on the first page.

Papers will be evaluated for originality, significance, clarity,
impact, and soundness. Each paper will be refereed by two experts
in the field who are independent of the conference program
committee.
The referees' evaluations will then be reviewed by two members of
the program committee who will recommend a decision to the co-
chairs.
The co-chairs will make the final decision. Lastly, the Camera-
Ready
papers will be reviewed by one member of the program committee.

PROPOSAL FOR ORGANIZING SESSIONS/WORKSHOPS:

Each session will have at least 6 paper presentations from
different authors (12 papers in the case of workshops). The
session chairs will be responsible for all aspects of their
sessions; including, soliciting papers, reviewing, selecting, ...
The names of session chairs will appear as Associate Editors in
the conference proceedings and on the cover of the books.

Proposals to organize sessions should include the following
information: name and address (+ email) of proposer, title of
session, a 100-word description of the topic of the session,
the name of the conference the session is submitted for
consideration (ie, EEE'09), and a short description on how
the session will be advertised (in most cases, session proposers
solicit papers from colleagues and researchers whose work is
known to the session proposer). email your session proposal
to Prof. Arabnia (address is given above). We would like to
receive the proposals by January 16, 2009.

IMPORTANT DATES:

Jan. 16, 2009: Proposals for organizing/chairing sessions/
workshops
Feb. 25, 2009: Submission of papers (about 5 to 7 pages)
March 25, 2009: Notification of acceptance
April 25, 2009: Camera-Ready papers and Registration due
July 13-16, 2009: The 2009 International Conference on e-Learning,
e-Business, Enterprise Information Systems, and
e-Government (EEE'09)

MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES:

The Program Committee includes members of chapters of World Academy
of Science (chapters: supercomputing; scientific computing; AI;
imaging science; databases; simulation; software engineering;
embedded systems; internet and web technologies; communications;
bioinformatics; computational biology; and computer security.)
The Program Committee for EEE is currently being formed. Those
interested in joining the Program Committee should email Prof.
Arabnia
(hra@cs.uga.edu) the following information: Name, affiliation
and position, complete mailing address, email address, a short
biography together with research interests and the name of the
conference (EEE) offering to help with.
Many who have already joined the committees of individual tracks
are renowned leaders, scholars, researchers, scientists and
practitioners of the highest ranks; many are directors of research
laboratories, fellows of various societies, heads/chairs of
departments, deans and provosts.

PURPOSE / HISTORY:

EEE'09 is an annual research conference about e-learning, e-
business,
enterprise information systems, and e-government.
It is being held jointly (same location and dates) with a number of
other conferences (WORLDCOMP'09). WORLDCOMP is the largest annual
gathering of researchers in computer science, computer engineering
and applied computing.

The motivation is to assemble a spectrum of affiliated research
topics
into a coordinated meeting held in a common place at a common time.
The main goal is to provide a forum for exchange of ideas in a
number
of research areas that interact. The model used facilitates
communication among researchers from all over the world in
different
fields of computer science, computer engineering and applied
computing. Both inward research (core areas of computer science
and
engineering) and outward research (multi-disciplinary, inter-
disciplinary,
and applications) will be covered during the event.

EEE'09 and WORLDCOMP'09 will be composed of research presentations,
keynote lectures, invited presentations, tutorials, panel
discussions,
and poster presentations. In recent past, keynote and/or tutorial
speakers included: Prof. David A. Patterson (U. of California,
Berkeley); Prof. Michael J. Flynn (Stanford U.); Prof. John H.
Holland
(U. of Michigan, Ann Arbor); Prof. Brian D. Athey (U. of Michigan,
Ann Arbor), Prof. H. J. Siegel (Colorado State U.); Prof. Barry
Vercoe
(MIT); Prof. Ruzena Bajcsy (U. of California, Berkeley);
Prof. Jun Liu (Harvard U.); Dr. Jim Gettys (OLPC + developer of X
Window); Dr. Chris Rowen (President and CEO, Tensilica, Inc.); and
many other distinguished speakers.

LOCATION OF CONFERENCES:

The conferences will be held in the Monte Carlo hotel, Las Vegas,
Nevada, USA (with any overflows at other near-by hotels). This is
a mega hotel with excellent conference facilities and over 3,000
rooms. It is minutes from the airport with 24-hour shuttle
service to and from the airport. This hotel has many recreational
attractions, including: waterfalls, spa, pools, sunning decks, Easy
River, wave pool, lighted tennis courts, health spa, nightly shows,
a number of restaurants, ... The negotiated room rate for
conference attendees is very reasonable. The hotel is within
walking distance from most other attractions (recreational
destinations, Golf courses, ...)

==============================================================================
TOPIC: what is memory addressing ?
http://groups.google.com/group/comp.programming.threads/t/12c59a69cdbcf172?hl=en
==============================================================================

== 1 of 3 ==
Date: Sat, Nov 29 2008 5:31 am
From: junee

well, I'm a bit confusing about memory addressing

lets see if the processor is 32bit

the maximum memory it can handle is 4294967296B

that's 4GB of memory.

how is this possible ?

can you please explain it, in an easy way ?

Thanks.

== 2 of 3 ==
Date: Sat, Nov 29 2008 6:40 am
From: David Schwartz

On Nov 29, 5:31 am, junee <azeez...@gmail.com> wrote:
> well, I'm a bit confusing about memory addressing
>
> lets see if the processor is 32bit
>
> the maximum memory it can handle is 4294967296B
>
> that's 4GB of memory.
>
> how is this possible ?
>
> can you please explain it, in an easy way ?
>
> Thanks.

If a process has a 32-bit memory bus, each bit of that bus can be in 2
possible states. With 32 address lines, each with 2 possible states,
there are 2^32 different possible addresses the bus can request. If
the addresses are byte addresses, then the CPU can address 2^32
different memory addresses.

However, typical 32-bit processors don't have 32-bit physical memory
buses. And calling a process a "32-bit processor" generally refers to
the operand word size, not the address bus size.

== 3 of 3 ==
Date: Sat, Nov 29 2008 5:16 pm
From: pjb@informatimago.com (Pascal J. Bourguignon)

junee <azeez541@gmail.com> writes:

> well, I'm a bit confusing about memory addressing
>
> lets see if the processor is 32bit
>
> the maximum memory it can handle is 4294967296 B
>
> that's 4GB of memory.
>
> how is this possible ?
>
> can you please explain it, in an easy way ?

Assume you have 1-bit addresses. Then you have two addresses, 0 and 1.
So you can have two memory slots, one at "address" 0, and another at
"address" 1.

Now, if you had 2-bit addresses, you would have four addresses: 00, 01,
10, and 11.

With 3-bit addresses, you'll get eight addresses: 000, 001, 010, 011,
100, 101, 110, and 111.

And so on...

2^1 = 2
2^2 = 4
2^3 = 8
2^4 = 16
...
2^32 = 4294967296

So when you reach 32-bit addresses, you can have 2^32 = 4294967296
memory slots.

Note that the amount of data stored in these memory slots is independant
of the size of the addresses. You may have any number of bits stored in
a memory slot.

In processors such as the 680x0 or ix86, you have 8-bit per memory
slots. But with other processors, you could have have 18 bits or 36
bits or 32 bits, or any number of bit really per memory slot.

But this is only the directly accessible memory. The computer may have
more memory available, and accessible indirectly, thru a memory
management unit, or with some simple paging hardware, with which the
processor can switch the accessible part of the memory (or "bank") by
setting some bits in some register.

And in addition, there could be permanent storage devices, such as a
hard disk, and the operating system could implement memory swapping,
where it stores memory temporarily not used to the disk and loads from
the disk data that it needs to use. So the addressable memory is not a
limit of the memory usable by the processor, you have to include the
swap memory. And why not, also the file system, and even the whole
Internet can be consired memory for a processor, as soon as it has a
network interface.

--
__Pascal Bourguignon__
http://www.informatimago.com

==============================================================================
TOPIC: Call for Papers: The 2009 International Conference on Parallel and
Distributed Processing Techniques and Applications (PDPTA'09), USA, July 13-16,
2009
http://groups.google.com/group/comp.programming.threads/t/7e024923f4068687?hl=en
==============================================================================

== 1 of 1 ==
Date: Sat, Nov 29 2008 9:21 pm
From: "A. M. G. Solo"

C A L L F O R P A P E R S
===============================

CALL FOR PAPERS
and
Call For Workshop/Session Proposals

The 2009 International Conference on Parallel and
Distributed Processing Techniques and Applications
PDPTA'09

Date and Location: July 13-16, 2009, Las Vegas, USA

You are invited to submit a paper (and/or a proposal to organize
a session/workshop). All accepted papers will be published in the
respective conference proceedings.

SCOPE: Topics of interest include, but are not limited to, the
following:

O Parallel/Distributed applications:
Numerical computations/methods, neural networks and
fuzzy logic, medicine, remote sensing, computer
vision, computer graphics and virtual reality,
parallel/distributed databases, banking, financial
markets, high-performance computational biology, ...
O Parallel/Distributed architectures:
Clusters and parallel systems of various topologies,
supercomputers, shared memory, distributed memory,
general- and special-purpose architectures,
instructional level parallelism, ...
O Networks and interconnection networks:
Scalable networks, reconfigurable networks, routing
issues, general-purpose network performance for
distributed applications, network protocols, internet
technology, optical interconnections and computing,
novel network topologies, ...
O Reliability and fault-tolerance:
Software and hardware fault-tolerance (system- and
application-level), fault diagnosis, fault-tolerance
measurement.
O Building block processors:
Applications of processors that can be used as basic
building blocks for multicomputer systems.
O Real-time and embedded systems:
Small-scale parallel systems for high-performance
control, data acquisition, and analysis; configuration,
routing, scheduling, performance guarantees, ...
O Parallel/Distributed algorithms:
Algorithms exploiting clusters and general-purpose
distributed and parallel systems, new vector/pipeline
issues, shared memory, distributed memory, virtual memory, ...
O Multimedia communications, systems, and applications:
High-speed networking, multimedia architectures and
protocols, multimedia applications, quality of service
support, operating system and networking support,
internet tools and applications, audio/video delivery
over the internet, ...
O Software tools and environments for parallel and
distributed platforms: operating systems, compilers,
languages, debuggers, monitoring tools, software
engineering on parallel/distributed systems, ...
O High-performance computing in computational science:
intra-disciplinary and multi-disciplinary research
programs and applications.
O Performance Evaluation and Management of Wireless Networks
and Distributed Systems
O FPGA-based design
O Performance analysis, evaluation, prediction, ...
O Nanotechnology in HPC
O High-performance mobile computation and communication.
O Object oriented technology and related issues.
O Scheduling and resource management.
O Petri Nets: theory, analysis, tools and applications.
O Web-based simulation and computing.
O Cloud computing
O Other aspects and applications relating to high-performance
computations
O Emerging technologies

Web links:
http://www.world-academy-of-science.org/worldcomp09/ws/conferences/pdpta09
http://www.world-academy-of-science.org/

ACADEMIC CO-SPONSORS:

Currently being prepared - it will include a number of active
research laboratories and centers that have helped to shape our
field. The Academic Co-Sponsors of the last offering of
PDPTA included research labs at Harvard University, UCLA,
University of Minnesota, University of Illinois at Urbana-
Champaign, Georgia Institute of Technology, Emory University,
University of Texas at Austin, MIT, George Mason University,
University of Iowa, Russian Academy of Sciences, NEMO/European
Union, and others. Corporate Co-Sponsors included, Google,
Salford Systems, Synplicity, Supermicro, NIIT, and others.

General Co-Chair and Coordinator:

Tel: (706) 542-3480
Fax: (706) 542-2966
E-mail: hra@cs.uga.edu

SUBMISSION OF PAPERS:

PROPOSAL FOR ORGANIZING SESSIONS/WORKSHOPS:

Proposals to organize sessions should include the following
information: name and address (+ email) of proposer, title of
session, a 100-word description of the topic of the session,
the name of the conference the session is submitted for
consideration (ie, PDPTA'09), and a short description on how
the session will be advertised (in most cases, session proposers
solicit papers from colleagues and researchers whose work is
known to the session proposer). email your session proposal
to Prof. Arabnia (address is given above). We would like to
receive the proposals by January 16, 2009.

IMPORTANT DATES:

Jan. 16, 2009: Proposals for organizing/chairing sessions/
workshops
Feb. 25, 2009: Submission of papers (about 5 to 7 pages)
March 25, 2009: Notification of acceptance
April 25, 2009: Camera-Ready papers and Registration due
July 13-16, 2009: The 2009 International Conference on Parallel
and
Distributed Processing Techniques and
Applications
(PDPTA'09)

MEMBERS OF PROGRAM AND ORGANIZING COMMITTEES:

The Program Committee includes members of chapters of World Academy
of Science (chapters: supercomputing; scientific computing; AI;
imaging science; databases; simulation; software engineering;
embedded systems; internet and web technologies; communications;
bioinformatics; computational biology; and computer security.)
The Program Committee for PDPTA is currently being formed. Those
interested in joining the Program Committee should email Prof.
Arabnia
(hra@cs.uga.edu) the following information: Name, affiliation
and position, complete mailing address, email address, a short
biography together with research interests and the name of the
conference (PDPTA) offering to help with.
Many who have already joined the committees of individual tracks
are renowned leaders, scholars, researchers, scientists and
practitioners of the highest ranks; many are directors of research
laboratories, fellows of various societies, heads/chairs of
departments, deans and provosts.

PURPOSE / HISTORY:

PDPTA'09 is an annual research conference about parallel and
distributed processing techniques and applications. It is being
held jointly (same location and dates) with a number of other
conferences (WORLDCOMP'09). WORLDCOMP is the largest annual
gathering of researchers in computer science, computer
engineering and applied computing.

PDPTA'09 and WORLDCOMP'09 will be composed of research
presentations,
keynote lectures, invited presentations, tutorials, panel
discussions,
and poster presentations. In recent past, keynote and/or tutorial
speakers included: Prof. David A. Patterson (U. of California,
Berkeley); Prof. Michael J. Flynn (Stanford U.); Prof. John H.
Holland
(U. of Michigan, Ann Arbor); Prof. Brian D. Athey (U. of Michigan,
Ann Arbor), Prof. H. J. Siegel (Colorado State U.); Prof. Barry
Vercoe
(MIT); Prof. Ruzena Bajcsy (U. of California, Berkeley);
Prof. Jun Liu (Harvard U.); Dr. Jim Gettys (OLPC + developer of X
Window); Dr. Chris Rowen (President and CEO, Tensilica, Inc.); and
many other distinguished speakers.

LOCATION OF CONFERENCES:

==============================================================================

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