Tuesday, November 19, 2019

Digest for comp.programming.threads@googlegroups.com - 3 updates in 2 topics

aminer68@gmail.com: Nov 18 02:26PM -0800

Hello..
 
 
Here is another problem with ARM processors..
 
 
About SC and TSO and RMO hardware memory models..
 
I have just read the following webpage about the performance difference
between: SC and TSO and RMO hardware memory models
 
I think TSO is better, it is just around 3% ~ 6% less performance
than RMO and it is a simpler programming model than RMO. So i think ARM
must support TSO to be compatible with x86 that is TSO.
 
Read more here to notice it:
 
https://infoscience.epfl.ch/record/201695/files/CS471_proj_slides_Tao_Marc_2011_1222_1.pdf
 
About memory models and sequential consistency:
 
As you have noticed i am working with x86 architecture..
 
Even though x86 gives up on sequential consistency, it's among the most
well-behaved architectures in terms of the crazy behaviors it allows.
Most other architectures implement even weaker memory models.
 
ARM memory model is notoriously underspecified, but is essentially a
form of weak ordering, which provides very few guarantees. Weak ordering
allows almost any operation to be reordered, which enables a variety of
hardware optimizations but is also a nightmare to program at the lowest
levels.
 
Read more here:
 
https://homes.cs.washington.edu/~bornholt/post/memory-models.html
 
 
Memory Models: x86 is TSO, TSO is Good
 
Essentially, the conclusion is that x86 in practice implements the old
SPARC TSO memory model.
 
The big take-away from the talk for me is that it confirms the
observation made may times before that SPARC TSO seems to be the optimal
memory model. It is sufficiently understandable that programmers can
write correct code without having barriers everywhere. It is
sufficiently weak that you can build fast hardware implementation that
can scale to big machines.
 
Read more here:
 
https://jakob.engbloms.se/archives/1435
 
 
Thank you,
Amine Moulay Ramdane.
aminer68@gmail.com: Nov 18 10:55AM -0800

Hello,
 
 
My Scalable VarFiler was updated to version 1.92
 
You can download it from:
 
https://sites.google.com/site/scalable68/scalable-parallel-varfiler
 
 
And the Scalable Varfiler benchmarks are here:
 
https://sites.google.com/site/scalable68/parallel-varfiler-benchmarks
 
 
 
Thank you,
Amine Moulay Ramdane.
aminer68@gmail.com: Nov 18 11:18AM -0800


> https://sites.google.com/site/scalable68/parallel-varfiler-benchmarks
 
> Thank you,
> Amine Moulay Ramdane.
 
 
Now ParallelVarFiler is Fault tolerant to power failures etc. i have done a simulation of power failures and data file damages and ParallelVarFiler is recovering from power failures and damages of the data file ...
 
If AnalyzeVarfiler() returns ctCorrupt if there is a power failure or something like that that gives a corruption, you have to fix the format of the archive with FixVarfiler() that will fix the format of the archive and recover from a power failure corruption etc.
 
 
Thank you,
Amine Moulay Ramdane.
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