Sunday, March 3, 2019

Digest for comp.lang.c++@googlegroups.com - 4 updates in 2 topics

"Chris M. Thomasson" <invalid_chris_thomasson_invalid@invalid.com>: Mar 02 08:56PM -0800

On 2/27/2019 7:25 AM, Scott Lurndal wrote:
> operating systems (which had, in 1985, mutex and condition variables
> built right into the instruction set) to modern pthread apps.
 
> http://vseries.lurndal.org/doku.php?id=instructions:lok
 
Afaict, std::shared_mutex should use native primitives that can beat my
loopless algorihtm in 100% pure C++. Except, sometimes it doesn't. My
contrived test, version 0.1, blasts the shi% out of the read/write
algorihtm with massive read/write contention. Designed to see how many
reads and writes occur when a centralized read/write mutex gets hammered
with contention for a fixed amount of time.
 
There is another class of algorihtm that should be thrown into the mix.
A special algorihtm in which readers are not dependent on writer
activity. Well, the test might have to be altered to represent a
read-mostly access pattern, instead of blasting with heavy writes and
reads. Humm...
"Chris M. Thomasson" <invalid_chris_thomasson_invalid@invalid.com>: Mar 02 09:08PM -0800

On 2/19/2019 10:49 PM, Chris M. Thomasson wrote:
> Fwiw, I wrote a crude new benchmark that measures how many reads and
> writes can be performed in a given amount of time.
 
[...]
 
I need to create another type of test, one that does not hammer things
so much wrt creating an equal amount of reader and writer threads. I
need to basically model a "read-mostly" work environment. Instead of a
hyper-hardcore read and write focused contention massacre...
"Chris M. Thomasson" <invalid_chris_thomasson_invalid@invalid.com>: Mar 03 01:43PM -0800

On 2/27/2019 2:25 AM, Bonita Montero wrote:
> But I think it's more elegant because more minimalistic when you realize
> that with the system facilities and have more than one implementation of
> the rw-mutex.
 
Just a little side note:
__________________________
Wrt porting your algorithm to 100% pure C++, I am a little bit worried
about performing shifts on a signed integer. Especially when you mutate
the "assumed" sign bit. Testing the value against zero: greater than,
less than, equal to, ect... After that: Well, it seems like UB, or
implementation defined behavior can occur...
__________________________
 
Port your algorithm to unsigned long. It is fairly straightforward, and
clears everything up.
Horizon68 <horizon@horizon.com>: Mar 03 01:07PM -0800

Hello..
 
 
About my scalable RWLocks that i have invented..
 
 
My Scalable RWLocks were updated to version 4.22
 
I have invented and added the following scalable algorithms of a
scalable Fast_RWLock and the scalable Fast_RWLockX that are
starvation-free and they are better than scalable Asymmetric RWLocks
that use IPIs, and they are costless on the reader side, so they are
really powerful, and they are now working with Windows and with Linux on
x86, i have tested them thoroughly and i think it is much more stable
and fast.
 
You can download them from my website here:
 
https://sites.google.com/site/scalable68/scalable-rwlock
 
 
But you have to also know that i have "invented" more "advanced"
scalable RWLocks that i will try to sell to Microsoft or to Embarcadero
or to Google software companies.
 
 
My scalable RWLocks inside the zipfile above are suitable for the
following systems that have a much bigger memory bandwidth and they
are suitable for NUMA systems, look here at the following systems:
 
https://www.anandtech.com/show/11544/intel-skylake-ep-vs-amd-epyc-7000-cpu-battle-of-the-decade/12
 
And my scalable RWLocks above, that i have invented , are suitable for
the following:
 
Based on Intel and Micron's claim, 3D Xpoint is 1000x faster than NAND
and 10x higher density than conventional memory (assume DRAM here). So
latency of PCIe NAND is about 100us, and 1000x faster 3D Xpoint gives
100ns, which is 2 times slower than DRAM's speed of 50ns, so this makes
my scalable RWLocks very useful for 3D Xpoint, so my scalable RWLocks
are for example very useful for Optane SSD 900P that uses 3D Xpoint and
thus they are very useful for such SSDs that use 3D XPoint and that are
used in a "scalable" RAID manner.
 
Read about Intel Optane SSD 900P Review: 3D XPoint Unleashed
 
https://www.tomshardware.co.uk/intel-optane-ssd-900p-3d-xpoint,review-34076.html
 
 
 
So Stay tunned !
 
 
 
Thank you,
Amine Moulay Ramdane.
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