- cmsg cancel <57984bd0-05f9-4533-a7d3-11e4e5ce394d@googlegroups.com> - 4 Updates
- About the store buffer and memory visibility.. - 1 Update
- More about memory visibility.. - 1 Update
- Artificial Intelligence: Mankind's Last Invention - 1 Update
- More about message passing.. - 1 Update
- Read again.. - 1 Update
- Why did Windows NT move away from the microkernel? - 1 Update
| Elephant Man <conanospamic@gmail.com>: Aug 14 06:13PM Article d'annulation posté via Nemo. |
| Elephant Man <conanospamic@gmail.com>: Aug 14 06:13PM Article d'annulation posté via Nemo. |
| Elephant Man <conanospamic@gmail.com>: Aug 14 06:13PM Article d'annulation posté via Nemo. |
| Elephant Man <conanospamic@gmail.com>: Aug 15 10:54AM Article d'annulation posté via Nemo. |
| aminer68@gmail.com: Aug 14 06:34PM -0700 Hello, About the store buffer and memory visibility.. I wrote before the following: ====================================================================== More about memory visibility.. I said before: As you know that in parallel programming you have to take care not only of memory ordering , but also take care about memory visibility, read this to notice it: A store barrier, "sfence" instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary. Read more here to understand correctly: "However under x86-TSO, the stores are cached in the store buffers, a load consult only shared memory and the store buffer of the given thread, wich means it can load data from memory and ignore values from the other thread." Read more here: https://books.google.ca/books?id=C2R2DwAAQBAJ&pg=PA127&lpg=PA127&dq=immediately+visible+and+m+fence+and+store+buffer+and+x86&source=bl&ots=yfGI17x1YZ&sig=ACfU3U2EYRawTkQmi3s5wY-sM7IgowDlWg&hl=en&sa=X&ved=2ahUKEwi_nq3duYPkAhVDx1kKHYoyA5UQ6AEwAnoECAgQAQ#v=onepage&q=immediately%20visible%20and%20m%20fence%20and%20store%20buffer%20and%20x86&f=false ======================================================================== Now can we ask the question of how much time takes the store buffer to drain ? So read here to notice: https://nicknash.me/2018/04/07/speculating-about-store-buffer-capacity/ So as you are noticing he is giving around 500 no-ops to allow the store buffer to drain, and i think that it can take less than that for the store buffer to drain, because i have noticed it in my scalable MLock when the store buffer draining time is amortized by the atomic CAS and by the time that it takes other cache-lines to transfer from core to core, here is my scalable MLock: https://sites.google.com/site/scalable68/scalable-mlock Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 14 04:51PM -0700 Hello, More about memory visibility.. I said before: As you know that in parallel programming you have to take care not only of memory ordering , but also take care about memory visibility, read this to notice it: A store barrier, "sfence" instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary. Read more here to understand correctly: "However under x86-TSO, the stores are cached in the store buffers, a load consult only shared memory and the store buffer of the given thread, wich means it can load data from memory and ignore values from the other thread." Read more here: https://books.google.ca/books?id=C2R2DwAAQBAJ&pg=PA127&lpg=PA127&dq=immediately+visible+and+m+fence+and+store+buffer+and+x86&source=bl&ots=yfGI17x1YZ&sig=ACfU3U2EYRawTkQmi3s5wY-sM7IgowDlWg&hl=en&sa=X&ved=2ahUKEwi_nq3duYPkAhVDx1kKHYoyA5UQ6AEwAnoECAgQAQ#v=onepage&q=immediately%20visible%20and%20m%20fence%20and%20store%20buffer%20and%20x86&f=false Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 14 12:11PM -0700 Hello, Look at this interesting video about artificial intelligence: Artificial Intelligence: Mankind's Last Invention https://www.youtube.com/watch?v=Pls_q2aQzHg Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 14 11:02AM -0700 Hello, More about message passing.. An advantage of shared memory model is that memory communication is faster as compared to the message passing model on the same machine. Read the following to notice it: "One problem that plagues microkernel implementations is relatively poor performance. The message-passing layer that connects different operating system components introduces an extra layer of machine instructions. The machine instruction overhead introduced by the message-passing subsystem manifests itself as additional execution time. In a monolithic system, if a kernel component needs to talk to another component, it can make direct function calls instead of going through a third party." Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 14 10:35AM -0700 Hello, An advantage of shared memory model is that memory communication is faster as compared to the message passing model on the same machine. Read the following to notice it: Why did Windows NT move away from the microkernel? "The main reason that Windows NT became a hybrid kernel is speed. A microkernel-based system puts only the bare minimum system components in the kernel and runs the rest of them as user mode processes, known as servers. A form of inter-process communication (IPC), usually message passing, is used for communication between servers and the kernel. Microkernel-based systems are more stable than others; if a server crashes, it can be restarted without affecting the entire system, which couldn't be done if every system component was part of the kernel. However, because of the overhead incurred by IPC and context-switching, microkernels are slower than traditional kernels. Due to the performance costs of a microkernel, Microsoft decided to keep the structure of a microkernel, but run the system components in kernel space. Starting in Windows Vista, some drivers are also run in user mode." Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 14 10:35AM -0700 Hello, An advantage of shared memory model is that memory communication is faster as compared to the message passing model on the same machine. Read the following to noticed it: Why did Windows NT move away from the microkernel? "The main reason that Windows NT became a hybrid kernel is speed. A microkernel-based system puts only the bare minimum system components in the kernel and runs the rest of them as user mode processes, known as servers. A form of inter-process communication (IPC), usually message passing, is used for communication between servers and the kernel. Microkernel-based systems are more stable than others; if a server crashes, it can be restarted without affecting the entire system, which couldn't be done if every system component was part of the kernel. However, because of the overhead incurred by IPC and context-switching, microkernels are slower than traditional kernels. Due to the performance costs of a microkernel, Microsoft decided to keep the structure of a microkernel, but run the system components in kernel space. Starting in Windows Vista, some drivers are also run in user mode." Thank you, Amine Moulay Ramdane. |
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