| aminer68@gmail.com: Aug 04 05:00PM -0700 Hello, I think that the future looks much more bright for parallel programming, because even if race conditions detection is NP-hard problem, there exist even "scalable" race detectors that become more and more powerful rapidly with the "exponential" growth of performance of scalable algorithms on parallel computers, look for example here to notice it : Scalable race detection for Android applications https://dl.acm.org/citation.cfm?id=2814303 I think deadlocks are much easier to detect. Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 04 02:46PM -0700 Hello, About the memory visibility problem and the solution.. As you have noticed i have just spoken about the memory visibility problem that gives also the race condition problem that is NP-hard, i think that to solve it , you have to manage global variables that are shared with a layer of message passing, and for example the queues of the message passing will issue a memory barrier so that to force visibility, but there is still a problem because this layer of message passing must detect the shared variables and so that to manage, but this layer needs to do it in an "exponential" time , because i think that this problem is exponential. So there is still a problem. Read the rest of my previous thoughts: More about race conditions and memory visibility: I said previously about the memory visibility problem the following: =============================================================== I have come to an interesting subject about memory visibility.. As you know that in parallel programming you have to take care not only of memory ordering , but also take care about memory visibility, read this to notice it: Store Barrier A store barrier, "sfence" instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary. I think that this is also the case in ARM CPUs and other CPUs.. So as you are noticing that i think that this memory visibility problem is rendering parallel programming more "difficult" and more "dangerous". What do you think about it ? ============================================================== I think this memory visibility problem can give race conditions, so this is a problem because read this about race conditions: NP-hard problem means there is no known algorithm can solve it in a polynomial time, so that the time to find a solution grows exponentially with problem size. Although it has not been definitively proven that, there is no polynomial algorithm for solving NP-hard problems, many eminent mathematicians have tried and failed. Race condition detection is NP-hard Read more here: https://pages.mtu.edu/~shene/NSF-3/e-Book/RACE/difficult.html Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 04 02:23PM -0700 Hello, More about race conditions and memory visibility: I said previously about the memory visibility problem the following: =============================================================== I have come to an interesting subject about memory visibility.. As you know that in parallel programming you have to take care not only of memory ordering , but also take care about memory visibility, read this to notice it: Store Barrier A store barrier, "sfence" instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary. I think that this is also the case in ARM CPUs and other CPUs.. So as you are noticing that i think that this memory visibility problem is rendering parallel programming more "difficult" and more "dangerous". What do you think about it ? ============================================================== I think this memory visibility problem can give race conditions, so this is a problem because read this about race conditions: NP-hard problem means there is no known algorithm can solve it in a polynomial time, so that the time to find a solution grows exponentially with problem size. Although it has not been definitively proven that, there is no polynomial algorithm for solving NP-hard problems, many eminent mathematicians have tried and failed. Race condition detection is NP-hard Read more here: https://pages.mtu.edu/~shene/NSF-3/e-Book/RACE/difficult.html Thank you, Amine Moulay Ramdane. |
| aminer68@gmail.com: Aug 04 01:39PM -0700 Hello, About memory visibility.. I have come to an interesting subject about memory visibility.. As you know that in parallel programming you have to take care not only of memory ordering , but also take care about memory visibility, read this to notice it: Store Barrier A store barrier, "sfence" instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued. This will make the program state "visible" to other CPUs so they can act on it if necessary. I think that this is also the case in ARM CPUs and other CPUs.. So as you are noticing that i think that this memory visibility problem is rendering parallel programming more "difficult" and more "dangerous". What do you think about it ? Thank you, Amine Moulay Ramdane. |
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