- DCAS-atomic - 4 Updates
| "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>: Jun 17 03:23PM -0700 On 6/17/2020 3:03 PM, Bonita Montero wrote: > Sorry, but youre talkin stupid stuff. I'm using the > MSVC / gcc intinsics, and both have full barriers. They do for x86. Well, except the acquire and release variants. See, Windows runs on different machines. ;^) > release- behaviour - logically from the view of the instruction > -stream as well as related to the internal order of the loads > and stores of the CPU. Where did I argue against that? I was just saying to think about programming for an arch that does not have implicit membars in its atomic RMW's. |
| "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>: Jun 17 03:23PM -0700 On 6/17/2020 3:02 PM, Bonita Montero wrote: > > Have you ever programmed for the SPARC in RMO mode or PPC? > > What about a DEC Alpha? > That are all dead CPUs. PPC is dead? |
| Bonita Montero <Bonita.Montero@gmail.com>: Jun 18 12:30AM +0200 > They do for x86. Well, except the acquire and release variants. They have acquire and release semantics for x86 and ARM. > Where did I argue against that? I was just saying to think about > programming for an arch that does not have implicit membars in its > atomic RMW's. My code runs with MSVC and gcc. And both have full membars with their CMPXCHG-intrinsics. So I don't know why you complain something here. |
| Bonita Montero <Bonita.Montero@gmail.com>: Jun 18 12:31AM +0200 >>> What about a DEC Alpha? >> That are all dead CPUs. > PPC is dead? Almost. It is mostly replaced in embedded-hardware by ARM-chips. |
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