- More of my philosophy about my way of doing and more of my thoughts.. - 1 Update
- Much more precision of my philosophy about quantum computing and about matrix operations and about scalability and more of my thoughts.. - 1 Update
- More of my philosophy about quantum computing and about matrix operations and about scalability and more of my thoughts.. - 1 Update
| Amine Moulay Ramdane <aminer68@gmail.com>: Nov 01 08:37PM -0700 Hello, More of my philosophy about my way of doing and more of my thoughts.. I am a white arab, and i think i am smart since i have also invented many scalable algorithms and algorithms.. What i am doing here is thinking very rapidly and writing very rapidly by making it like clever thinking and by efficiently minimizing errors and mistakes, and it is my way of doing so that to show my kind of efficiency and my kind of personality, since if i think less rapidly, i can be much more efficient, so it is like a smart game that i am playing smartly, so i invite you to also read all my following thoughts in the following web links that i have just thought very rapidly and just written very rapidly and posted here: More of my philosophy about my contributions and more of my thoughts.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, and now you are knowing more about my contributions here, for example i have invented a new philosophy and many proverbs and many poems of Love and poems, you can take a look at them in the following web link: https://groups.google.com/g/alt.culture.morocco/c/WDPcc45utLQ Also i have just invented quickly another new religion, so i have invented two religions, one not monotheistic religion and another monotheistic religion, so here is my just new not monotheistic religion, you can read about it in the following web link: https://groups.google.com/g/alt.culture.morocco/c/Ad2tRwDxdjA And here is my other monotheistic religion that i have invented(click on the "Amine Moulay Ramdane" post so that to read it): https://groups.google.com/g/soc.culture.usa/c/vKBlK160YR0 And of course you can read my thoughts about technology in the following web link: https://groups.google.com/g/soc.culture.usa/c/N_UxX3OECX4 Also you can read my new writing about new interesting medical treatments and drugs and about antibiotic resistance here: https://groups.google.com/g/alt.culture.morocco/c/vChmXT_pXUI More of my philosophy about quantum computing and about matrix operations and about scalability and more of my thoughts.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, i have just looked at the following video about the powerful parallel quantum computer of IBM from USA that will be soon available in the cloud, and i invite you to look at it: Quantum Computing: Now Widely Available! https://www.youtube.com/watch?v=laqpfQ8-jFI But i have just read the following paper and it saying that the powerful Quantum algorithms for matrix operations and linear systems of equations are available, read about them on the below paper, so as you notice in the following paper that many matrix operations and also the linear systems of equations solver can be done in a quantum computer, read about it here in the following paper: Quantum algorithms for matrix operations and linear systems of equations Read more here: https://arxiv.org/pdf/2202.04888.pdf So i think that IBM will do the same for there powerful parallel quantum computer that will be available in the cloud, but i think that you will have to pay for it of course since i think it will be commercial, but i think that there is a weakness with this kind of configuration of the powerful parallel quantum computer from IBM, since the cost of bandwidth of internet is exponentially decreasing , but the latency of accessing the internet is not, so it is why i think that people will still use classical computers for many mathematical applications that uses mathematical operations such as matrix operations and linear systems of equations etc. that needs a much faster latency, other than that Moore's law will still be effective in classical computers since it will permit us to have really powerful classical computer at a low cost and it will be really practical since the quantum computer is big in size and not so practical, so read about the two inventions below that will make logic gates thousands of times faster or a million times faster than those in existing computers so that to notice it, so i think that the business of classical computers will still be great in the future even with the coming of the powerful parallel quantum computer of IBM, so as you notice this kind of business is not only dependent on Moore's law and Bezos' Law , but it is also dependent on the latency of accessing internet, so read my following thoughts about Moore's law and about Bezos' Law: More of my philosophy about Moore's law and about Bezos' Law.. For RAM chips and flash memory, Moore's Law means that in eighteen months you'll pay the same price as today for twice as much storage. But other computing components are also seeing their price versus performance curves skyrocket exponentially. Data storage doubles every twelve months. More about Moore's law and about Bezos' Law.. "Parallel code is the recipe for unlocking Moore's Law" And: "BEZOS' LAW The Cost of Cloud Computing will be cut in half every 18 months - Bezos' Law Like Moore's law, Bezos' Law is about exponential improvement over time. If you look at AWS history, they drop prices constantly. In 2013 alone they've already had 9 price drops. The difference; however, between Bezos' and Moore's law is this: Bezos' law is the first law that isn't anchored in technical innovation. Rather, Bezos' law is anchored in confidence and market dynamics, and will only hold true so long as Amazon is not the aggregate dominant force in Cloud Computing (50%+ market share). Monopolies don't cut prices." More of my philosophy about latency and contention and concurrency and parallelism and more of my thoughts.. I think i am highly smart and i have just posted, read it below, about the new two inventions that will make logic gates thousands of times faster or a million times faster than those in existing computers, and i think that there is still a problem with those new inventions, and it is about the latency and concurrency, since you need concurrency and you need preemptive or non-preemptive scheduling of the coroutines , so since the HBM is 106.7 ns in latency and the DDR4 is 73.3 ns in latency and the AMD 3D V-Cache has also almost the same cost in latency, so as you notice that this kind of latency is still costly , also there is a latency that is the Time slice that takes a coroutine to execute and it is costly in latency, since this kind of latency and Time slice is a waiting time that looks like the time wasted in a contention in parallelism, so by logical analogy this kind of latency and Time slice create like a contention like in parallelism that reduces scalability, so i think it is why those new inventions have this kind of limit or constraints in a "concurrency" environment. And i invite you to read my following smart thoughts about preemptive and non-preemptive timesharing: https://groups.google.com/g/alt.culture.morocco/c/JuC4jar661w More of my philosophy about Fastest-ever logic gates and more of my thoughts.. "Logic gates are the fundamental building blocks of computers, and researchers at the University of Rochester have now developed the fastest ones ever created. By zapping graphene and gold with laser pulses, the new logic gates are a million times faster than those in existing computers, demonstrating the viability of "lightwave electronics.". If these kinds of lightwave electronic devices ever do make it to market, they could be millions of times faster than today's computers. Currently we measure processing speeds in Gigahertz (GHz), but these new logic gates function on the scale of Petahertz (PHz). Previous studies have set that as the absolute quantum limit of how fast light-based computer systems could possibly get." Read more here: https://newatlas.com/electronics/fastest-ever-logic-gates-computers-million-times-faster-petahertz/ Read my following news: And with the following new discovery computers and phones could run thousands of times faster.. Prof Alan Dalton in the School of Mathematical and Physics Sciences at the University of Sussex, said: "We're mechanically creating kinks in a layer of graphene. It's a bit like nano-origami. "Using these nanomaterials will make our computer chips smaller and faster. It is absolutely critical that this happens as computer manufacturers are now at the limit of what they can do with traditional semiconducting technology. Ultimately, this will make our computers and phones thousands of times faster in the future. "This kind of technology -- "straintronics" using nanomaterials as opposed to electronics -- allows space for more chips inside any device. Everything we want to do with computers -- to speed them up -- can be done by crinkling graphene like this." Dr Manoj Tripathi, Research Fellow in Nano-structured Materials at the University of Sussex and lead author on the paper, said: "Instead of having to add foreign materials into a device, we've shown we can create structures from graphene and other 2D materials simply by adding deliberate kinks into the structure. By making this sort of corrugation we can create a smart electronic component, like a transistor, or a logic gate." The development is a greener, more sustainable technology. Because no additional materials need to be added, and because this process works at room temperature rather than high temperature, it uses less energy to create. Read more here: https://www.sciencedaily.com/releases/2021/02/210216100141.htm But I think that mass production of graphene still hasn't quite begun, so i think the inventions above of the Fastest-ever logic gates that uses graphene and of the one with nanomaterials that uses graphene will not be commercialized fully until perhaps around year 2035 or 2040 or so, so read the following so that to understand why: "Because large-scale mass production of graphene still hasn't quite begun , the market is a bit limited. However, that leaves a lot of room open for investors to get in before it reaches commercialization. The market was worth $78.7 million in 2019 and, according to Grand View Research, is expected to rise drastically to $1.08 billion by 2027. North America currently has the bulk of market share, but the Asia-Pacific area is expected to have the quickest growth in adoption of graphene uses in coming years. North America and Europe are also expected to have above-market average growth. The biggest driver of all this growth is expected to be the push for cleaner, more efficient energy sources and the global reduction of emissions in the air." Read more here: https://www.energyandcapital.com/report/the-worlds-next-rare-earth-metal/1600 And of course you can read my thoughts about technology in the following web link: https://groups.google.com/g/soc.culture.usa/c/N_UxX3OECX4 More of my philosophy about matrix-matrix multiplication and about scalability and more of my thoughts.. I think that the time complexity of the Strassen algorithm for matrix-matrix multiplication is around O(N^2.8074), and the time complexity of the naive algorithm is O(N^3) , so it is not a significant difference, so i think i will soon implement the parallel Blocked matrix-matrix multiplication and i will implement it with a new algorithm that also uses intel AVX512 and that uses fused multiply-add and of course it will use the assembler instructions below of prefetching into caches so that to gain a 22% speed, so i think that overall it will have around the same speed as parallel BLAS, and i say that Pipelining greatly increases throughput in modern CPUs such as x86 CPUs, and another common pipelining scenario is the FMA or fused multiply-add, which is a fundamental part of the instruction set for some processors. The basic load-operate-store sequence simply lengthens by one step to become load-multiply-add-store. The FMA is possible only if the hardware supports it, as it does in the case of the Intel Xeon Phi, for example, as well as in Skylake etc. More of my philosophy about matrix-vector multiplication of large matrices and about scalability and more of my thoughts.. The matrix-vector multiplication of large matrices is completly limited by the memory bandwidth as i have just said it, read it below, so vector extensions like using SSE or AVX are usually not necessary for matrix-vector multiplication of large matrices. It is interesting that matrix-matrix-multiplications don't have these kind of problems with memory bandwidth. Companies like Intel or AMD typically usually show benchmarks of matrix-matrix multiplications and they show how nice they scale on many more cores, but they never show matrix-vector multiplications, and notice that my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also memory-bound and the matrices for it are usually big, but my new algorithm of it is efficiently cache-aware and efficiently NUMA-aware, and i have implemented it for the dense and sparse matrices. More of my philosophy about the efficient Matrix-Vector multiplication algorithm in MPI and about scalability and more of my thoughts.. Matrix-vector multiplication is an absolutely fundamental operation, with countless applications in computer science and scientific computing. Efficient algorithms for matrix-vector multiplication are of paramount importance, and notice that for matrix-vector multiplication, n^2 time is certainly required for an n × n dense matrix, but you have to be smart, since in MPI computing for also the supercomputer exascale systems, doesn't only take into account this n^2 time, since it has to also be efficiently be cache-aware, and it has to also have a good complexity for the how much memory is used by the parallel processes in MPI, since notice carefully with me that you have also to not send both a row of the matrix and the vector the the parallel processes of MPI, but you have to know how to reduce efficiently this complexity by for example dividing each row of the matrix and by dividing the vector and sending a part of the row of the matrix and a part of the vector to the parallel processes of MPI, and i think that in an efficient algorithm for Matrix-Vector multiplication, time for addition is dominated by the communication time, and of course that my implementation of my Powerful Open source software of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also smart, since it is efficiently cache-aware and efficiently NUMA-aware, and it implements both the dense and the sparse, and of course as i am showing below, it is scaling well on the memory channels, so it is scaling well in my 16 cores dual Xeon with 8 memory channels as i am showing below, and it will scale well on 16 sockets HPE NONSTOP X SYSTEMS or the 16 sockets HPE Integrity Superdome X with above 512 cores and with 64 memory channels, so i invite you to read carefully and to download my Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well from my website here: https://sites.google.com/site/scalable68/scalable-parallel-c-conjugate-gradient-linear-system-solver-library MPI will continue to be a viable programming model on exascale supercomputer systems, so i will soon implement many algorithms in MPI for Delphi and Freepascal and i will provide you with them, i am currently implementing an efficient Matrix-Vector multiplication algorithm in MPI and you have to know that an efficient Matrix-Vector multiplication algorithm is really important for scientific applications, and of course i will also soon implement many other interesting |
| Amine Moulay Ramdane <aminer68@gmail.com>: Nov 01 05:20PM -0700 Hello, Much more precision of my philosophy about quantum computing and about matrix operations and about scalability and more of my thoughts.. I am a white arab, and i think i am smart since i have also invented many scalable algorithms and algorithms.. Read my following thoughts , since i have just brought much more precision to them: I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, i have just looked at the following video about the powerful parallel quantum computer of IBM from USA that will be soon available in the cloud, and i invite you to look at it: Quantum Computing: Now Widely Available! https://www.youtube.com/watch?v=laqpfQ8-jFI But i have just read the following paper and it saying that the powerful Quantum algorithms for matrix operations and linear systems of equations are available, read about them on the below paper, so as you notice in the following paper that many matrix operations and also the linear systems of equations solver can be done in a quantum computer, read about it here in the following paper: Quantum algorithms for matrix operations and linear systems of equations Read more here: https://arxiv.org/pdf/2202.04888.pdf So i think that IBM will do the same for there powerful parallel quantum computer that will be available in the cloud, but i think that you will have to pay for it of course since i think it will be commercial, but i think that there is a weakness with this kind of configuration of the powerful parallel quantum computer from IBM, since the cost of bandwidth of internet is exponentially decreasing , but the latency of accessing the internet is not, so it is why i think that people will still use classical computers for many mathematical applications that uses mathematical operations such as matrix operations and linear systems of equations etc. that needs a much faster latency, other than that Moore's law will still be effective in classical computers since it will permit us to have really powerful classical computer at a low cost and it will be really practical since the quantum computer is big in size that and not so practical, so read about the two inventions below that will make logic gates thousands of times faster or a million times faster than those in existing computers so that to notice it, so i think that the business of classical computers will still be great in the future even with the coming of the powerful parallel quantum computer of IBM, so as you notice this kind of business is not only dependent on Moore's law and Bezos' Law , but it is also dependent on the latency of accessing internet, so read my following thoughts about Moore's law and about Bezos' Law: More of my philosophy about Moore's law and about Bezos' Law.. For RAM chips and flash memory, Moore's Law means that in eighteen months you'll pay the same price as today for twice as much storage. But other computing components are also seeing their price versus performance curves skyrocket exponentially. Data storage doubles every twelve months. More about Moore's law and about Bezos' Law.. "Parallel code is the recipe for unlocking Moore's Law" And: "BEZOS' LAW The Cost of Cloud Computing will be cut in half every 18 months - Bezos' Law Like Moore's law, Bezos' Law is about exponential improvement over time. If you look at AWS history, they drop prices constantly. In 2013 alone they've already had 9 price drops. The difference; however, between Bezos' and Moore's law is this: Bezos' law is the first law that isn't anchored in technical innovation. Rather, Bezos' law is anchored in confidence and market dynamics, and will only hold true so long as Amazon is not the aggregate dominant force in Cloud Computing (50%+ market share). Monopolies don't cut prices." More of my philosophy about latency and contention and concurrency and parallelism and more of my thoughts.. I think i am highly smart and i have just posted, read it below, about the new two inventions that will make logic gates thousands of times faster or a million times faster than those in existing computers, and i think that there is still a problem with those new inventions, and it is about the latency and concurrency, since you need concurrency and you need preemptive or non-preemptive scheduling of the coroutines , so since the HBM is 106.7 ns in latency and the DDR4 is 73.3 ns in latency and the AMD 3D V-Cache has also almost the same cost in latency, so as you notice that this kind of latency is still costly , also there is a latency that is the Time slice that takes a coroutine to execute and it is costly in latency, since this kind of latency and Time slice is a waiting time that looks like the time wasted in a contention in parallelism, so by logical analogy this kind of latency and Time slice create like a contention like in parallelism that reduces scalability, so i think it is why those new inventions have this kind of limit or constraints in a "concurrency" environment. And i invite you to read my following smart thoughts about preemptive and non-preemptive timesharing: https://groups.google.com/g/alt.culture.morocco/c/JuC4jar661w More of my philosophy about Fastest-ever logic gates and more of my thoughts.. "Logic gates are the fundamental building blocks of computers, and researchers at the University of Rochester have now developed the fastest ones ever created. By zapping graphene and gold with laser pulses, the new logic gates are a million times faster than those in existing computers, demonstrating the viability of "lightwave electronics.". If these kinds of lightwave electronic devices ever do make it to market, they could be millions of times faster than today's computers. Currently we measure processing speeds in Gigahertz (GHz), but these new logic gates function on the scale of Petahertz (PHz). Previous studies have set that as the absolute quantum limit of how fast light-based computer systems could possibly get." Read more here: https://newatlas.com/electronics/fastest-ever-logic-gates-computers-million-times-faster-petahertz/ Read my following news: And with the following new discovery computers and phones could run thousands of times faster.. Prof Alan Dalton in the School of Mathematical and Physics Sciences at the University of Sussex, said: "We're mechanically creating kinks in a layer of graphene. It's a bit like nano-origami. "Using these nanomaterials will make our computer chips smaller and faster. It is absolutely critical that this happens as computer manufacturers are now at the limit of what they can do with traditional semiconducting technology. Ultimately, this will make our computers and phones thousands of times faster in the future. "This kind of technology -- "straintronics" using nanomaterials as opposed to electronics -- allows space for more chips inside any device. Everything we want to do with computers -- to speed them up -- can be done by crinkling graphene like this." Dr Manoj Tripathi, Research Fellow in Nano-structured Materials at the University of Sussex and lead author on the paper, said: "Instead of having to add foreign materials into a device, we've shown we can create structures from graphene and other 2D materials simply by adding deliberate kinks into the structure. By making this sort of corrugation we can create a smart electronic component, like a transistor, or a logic gate." The development is a greener, more sustainable technology. Because no additional materials need to be added, and because this process works at room temperature rather than high temperature, it uses less energy to create. Read more here: https://www.sciencedaily.com/releases/2021/02/210216100141.htm But I think that mass production of graphene still hasn't quite begun, so i think the inventions above of the Fastest-ever logic gates that uses graphene and of the one with nanomaterials that uses graphene will not be commercialized fully until perhaps around year 2035 or 2040 or so, so read the following so that to understand why: "Because large-scale mass production of graphene still hasn't quite begun , the market is a bit limited. However, that leaves a lot of room open for investors to get in before it reaches commercialization. The market was worth $78.7 million in 2019 and, according to Grand View Research, is expected to rise drastically to $1.08 billion by 2027. North America currently has the bulk of market share, but the Asia-Pacific area is expected to have the quickest growth in adoption of graphene uses in coming years. North America and Europe are also expected to have above-market average growth. The biggest driver of all this growth is expected to be the push for cleaner, more efficient energy sources and the global reduction of emissions in the air." Read more here: https://www.energyandcapital.com/report/the-worlds-next-rare-earth-metal/1600 And of course you can read my thoughts about technology in the following web link: https://groups.google.com/g/soc.culture.usa/c/N_UxX3OECX4 More of my philosophy about matrix-matrix multiplication and about scalability and more of my thoughts.. I think that the time complexity of the Strassen algorithm for matrix-matrix multiplication is around O(N^2.8074), and the time complexity of the naive algorithm is O(N^3) , so it is not a significant difference, so i think i will soon implement the parallel Blocked matrix-matrix multiplication and i will implement it with a new algorithm that also uses intel AVX512 and that uses fused multiply-add and of course it will use the assembler instructions below of prefetching into caches so that to gain a 22% speed, so i think that overall it will have around the same speed as parallel BLAS, and i say that Pipelining greatly increases throughput in modern CPUs such as x86 CPUs, and another common pipelining scenario is the FMA or fused multiply-add, which is a fundamental part of the instruction set for some processors. The basic load-operate-store sequence simply lengthens by one step to become load-multiply-add-store. The FMA is possible only if the hardware supports it, as it does in the case of the Intel Xeon Phi, for example, as well as in Skylake etc. More of my philosophy about matrix-vector multiplication of large matrices and about scalability and more of my thoughts.. The matrix-vector multiplication of large matrices is completly limited by the memory bandwidth as i have just said it, read it below, so vector extensions like using SSE or AVX are usually not necessary for matrix-vector multiplication of large matrices. It is interesting that matrix-matrix-multiplications don't have these kind of problems with memory bandwidth. Companies like Intel or AMD typically usually show benchmarks of matrix-matrix multiplications and they show how nice they scale on many more cores, but they never show matrix-vector multiplications, and notice that my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also memory-bound and the matrices for it are usually big, but my new algorithm of it is efficiently cache-aware and efficiently NUMA-aware, and i have implemented it for the dense and sparse matrices. More of my philosophy about the efficient Matrix-Vector multiplication algorithm in MPI and about scalability and more of my thoughts.. Matrix-vector multiplication is an absolutely fundamental operation, with countless applications in computer science and scientific computing. Efficient algorithms for matrix-vector multiplication are of paramount importance, and notice that for matrix-vector multiplication, n^2 time is certainly required for an n × n dense matrix, but you have to be smart, since in MPI computing for also the supercomputer exascale systems, doesn't only take into account this n^2 time, since it has to also be efficiently be cache-aware, and it has to also have a good complexity for the how much memory is used by the parallel processes in MPI, since notice carefully with me that you have also to not send both a row of the matrix and the vector the the parallel processes of MPI, but you have to know how to reduce efficiently this complexity by for example dividing each row of the matrix and by dividing the vector and sending a part of the row of the matrix and a part of the vector to the parallel processes of MPI, and i think that in an efficient algorithm for Matrix-Vector multiplication, time for addition is dominated by the communication time, and of course that my implementation of my Powerful Open source software of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also smart, since it is efficiently cache-aware and efficiently NUMA-aware, and it implements both the dense and the sparse, and of course as i am showing below, it is scaling well on the memory channels, so it is scaling well in my 16 cores dual Xeon with 8 memory channels as i am showing below, and it will scale well on 16 sockets HPE NONSTOP X SYSTEMS or the 16 sockets HPE Integrity Superdome X with above 512 cores and with 64 memory channels, so i invite you to read carefully and to download my Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well from my website here: https://sites.google.com/site/scalable68/scalable-parallel-c-conjugate-gradient-linear-system-solver-library MPI will continue to be a viable programming model on exascale supercomputer systems, so i will soon implement many algorithms in MPI for Delphi and Freepascal and i will provide you with them, i am currently implementing an efficient Matrix-Vector multiplication algorithm in MPI and you have to know that an efficient Matrix-Vector multiplication algorithm is really important for scientific applications, and of course i will also soon implement many other interesting algorithms in MPI for Delphi and Freepascal and i will provide you with them, so stay tuned ! More of my philosophy about the memory bottleneck and about scalability and more of my thoughts.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, and I am also specialized in parallel computing, and i know that the large cache can reduce Amdahl's Law bottleneck – main memory, but you have to understand what i am saying, since my Open source project below of my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also memory-bound and the matrices for it are usually big, and since also the sparse linear system solvers are ubiquitous in high performance computing (HPC) and often are the most computational intensive parts in scientific computing codes. A few of the many applications relying on sparse linear solvers include fusion energy simulation, space weather simulation, climate modeling, and environmental modeling, and finite element method, and large-scale reservoir simulations to enhance oil recovery by the oil and gas industry. So it is why i am speaking about the how many memory channels comes in the 16 sockets HPE NONSTOP X SYSTEMS or the 16 sockets HPE Integrity Superdome X, so as you notice that they can come with more than 512 cores and with 64 memory channels. Also i have just benchmarked my Scalable Varfiler and it is scaling above 7x on my 16 cores Dual Xeon processor, and it is scaling well since i have 8 memory channels, and i invite you to look at my powerful Scalable Varfiler carefully in the following web link: https://sites.google.com/site/scalable68/scalable-parallel-varfiler More of my philosophy about the how many memory channels in the 16 sockets HPE |
| Amine Moulay Ramdane <aminer68@gmail.com>: Nov 01 04:12PM -0700 Hello, More of my philosophy about quantum computing and about matrix operations and about scalability and more of my thoughts.. I am a white arab, and i think i am smart since i have also invented many scalable algorithms and algorithms.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, i have just looked at the following video about the powerful parallel quantum computer of IBM from USA that will be soon available in the cloud, and i invite you to look at it: Quantum Computing: Now Widely Available! https://www.youtube.com/watch?v=laqpfQ8-jFI But i have just read the following paper and it saying that the powerful Quantum algorithms for matrix operations and linear systems of equations are available, read about them on the above paper, so as you notice in the following paper that many matrix operations and also the linear systems of equations solver can be done in a quantum computer, read about it here in the following paper: Quantum algorithms for matrix operations and linear systems of equations Read more here: https://arxiv.org/pdf/2202.04888.pdf So i think that IBM will do the same for there powerful parallel quantum computer that will be available in the cloud, but i think that you will have to pay for it of course since i think it will be commercial, but i think that there is a weakness with this kind of configuration of the powerful quantum computer from IBM, since the cost of bandwidth of internet is exponentially decreasing , but the latency of accessing the internet is not, so it is why i think that people will still use classical computers for many mathematical applications that uses mathematical operations such as matrix operations and linear systems of equations etc. that needs a much faster latency, so i think that the business of classical computers will still be great in the future even with the coming of the powerful parallel quantum computer of IBM, so as you notice this kind of business is not only dependent on Moore's law and Bezos' Law , but it is also dependent on the latency of accessing internet, so read my following thoughts about Moore's law and about Bezos' Law: More of my philosophy about Moore's law and about Bezos' Law.. For RAM chips and flash memory, Moore's Law means that in eighteen months you'll pay the same price as today for twice as much storage. But other computing components are also seeing their price versus performance curves skyrocket exponentially. Data storage doubles every twelve months. More about Moore's law and about Bezos' Law.. "Parallel code is the recipe for unlocking Moore's Law" And: "BEZOS' LAW The Cost of Cloud Computing will be cut in half every 18 months - Bezos' Law Like Moore's law, Bezos' Law is about exponential improvement over time. If you look at AWS history, they drop prices constantly. In 2013 alone they've already had 9 price drops. The difference; however, between Bezos' and Moore's law is this: Bezos' law is the first law that isn't anchored in technical innovation. Rather, Bezos' law is anchored in confidence and market dynamics, and will only hold true so long as Amazon is not the aggregate dominant force in Cloud Computing (50%+ market share). Monopolies don't cut prices." More of my philosophy about matrix-matrix multiplication and about scalability and more of my thoughts.. I think that the time complexity of the Strassen algorithm for matrix-matrix multiplication is around O(N^2.8074), and the time complexity of the naive algorithm is O(N^3) , so it is not a significant difference, so i think i will soon implement the parallel Blocked matrix-matrix multiplication and i will implement it with a new algorithm that also uses intel AVX512 and that uses fused multiply-add and of course it will use the assembler instructions below of prefetching into caches so that to gain a 22% speed, so i think that overall it will have around the same speed as parallel BLAS, and i say that Pipelining greatly increases throughput in modern CPUs such as x86 CPUs, and another common pipelining scenario is the FMA or fused multiply-add, which is a fundamental part of the instruction set for some processors. The basic load-operate-store sequence simply lengthens by one step to become load-multiply-add-store. The FMA is possible only if the hardware supports it, as it does in the case of the Intel Xeon Phi, for example, as well as in Skylake etc. More of my philosophy about matrix-vector multiplication of large matrices and about scalability and more of my thoughts.. The matrix-vector multiplication of large matrices is completly limited by the memory bandwidth as i have just said it, read it below, so vector extensions like using SSE or AVX are usually not necessary for matrix-vector multiplication of large matrices. It is interesting that matrix-matrix-multiplications don't have these kind of problems with memory bandwidth. Companies like Intel or AMD typically usually show benchmarks of matrix-matrix multiplications and they show how nice they scale on many more cores, but they never show matrix-vector multiplications, and notice that my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also memory-bound and the matrices for it are usually big, but my new algorithm of it is efficiently cache-aware and efficiently NUMA-aware, and i have implemented it for the dense and sparse matrices. More of my philosophy about the efficient Matrix-Vector multiplication algorithm in MPI and about scalability and more of my thoughts.. Matrix-vector multiplication is an absolutely fundamental operation, with countless applications in computer science and scientific computing. Efficient algorithms for matrix-vector multiplication are of paramount importance, and notice that for matrix-vector multiplication, n^2 time is certainly required for an n × n dense matrix, but you have to be smart, since in MPI computing for also the supercomputer exascale systems, doesn't only take into account this n^2 time, since it has to also be efficiently be cache-aware, and it has to also have a good complexity for the how much memory is used by the parallel processes in MPI, since notice carefully with me that you have also to not send both a row of the matrix and the vector the the parallel processes of MPI, but you have to know how to reduce efficiently this complexity by for example dividing each row of the matrix and by dividing the vector and sending a part of the row of the matrix and a part of the vector to the parallel processes of MPI, and i think that in an efficient algorithm for Matrix-Vector multiplication, time for addition is dominated by the communication time, and of course that my implementation of my Powerful Open source software of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also smart, since it is efficiently cache-aware and efficiently NUMA-aware, and it implements both the dense and the sparse, and of course as i am showing below, it is scaling well on the memory channels, so it is scaling well in my 16 cores dual Xeon with 8 memory channels as i am showing below, and it will scale well on 16 sockets HPE NONSTOP X SYSTEMS or the 16 sockets HPE Integrity Superdome X with above 512 cores and with 64 memory channels, so i invite you to read carefully and to download my Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well from my website here: https://sites.google.com/site/scalable68/scalable-parallel-c-conjugate-gradient-linear-system-solver-library MPI will continue to be a viable programming model on exascale supercomputer systems, so i will soon implement many algorithms in MPI for Delphi and Freepascal and i will provide you with them, i am currently implementing an efficient Matrix-Vector multiplication algorithm in MPI and you have to know that an efficient Matrix-Vector multiplication algorithm is really important for scientific applications, and of course i will also soon implement many other interesting algorithms in MPI for Delphi and Freepascal and i will provide you with them, so stay tuned ! More of my philosophy about the memory bottleneck and about scalability and more of my thoughts.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, and I am also specialized in parallel computing, and i know that the large cache can reduce Amdahl's Law bottleneck – main memory, but you have to understand what i am saying, since my Open source project below of my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well is also memory-bound and the matrices for it are usually big, and since also the sparse linear system solvers are ubiquitous in high performance computing (HPC) and often are the most computational intensive parts in scientific computing codes. A few of the many applications relying on sparse linear solvers include fusion energy simulation, space weather simulation, climate modeling, and environmental modeling, and finite element method, and large-scale reservoir simulations to enhance oil recovery by the oil and gas industry. So it is why i am speaking about the how many memory channels comes in the 16 sockets HPE NONSTOP X SYSTEMS or the 16 sockets HPE Integrity Superdome X, so as you notice that they can come with more than 512 cores and with 64 memory channels. Also i have just benchmarked my Scalable Varfiler and it is scaling above 7x on my 16 cores Dual Xeon processor, and it is scaling well since i have 8 memory channels, and i invite you to look at my powerful Scalable Varfiler carefully in the following web link: https://sites.google.com/site/scalable68/scalable-parallel-varfiler More of my philosophy about the how many memory channels in the 16 sockets HPE NONSTOP X SYSTEMS and more of my thoughts.. I think i was right by saying that the 16 sockets HPE NONSTOP X SYSTEMS or the 16 sockets HPE Integrity Superdome X have around 2 to 4 memory channels per socket on x86 with Intel Xeons, and it means that they have 32 or 64 memory channels. You can read here the FAQ from Hewlett Packard Enterprise from USA so that to notice it: https://bugzilla.redhat.com/show_bug.cgi?id=1346327 And it says the following: "How many memory channels per socket for specific CPU? Each of the 8 blades has 2 CPU sockets. Each CPU socket has 2 memory channels each connecting to 2 memory controllers that contain 6 Dimms each." So i think that it can also support 4 memory channels per CPU socket with Intel Xeons. More of my philosophy about the highest availability with HPE NONSTOP X SYSTEMS from Hewlett Packard Enterprise from USA and more of my thoughts.. I have just talked, read it below, about the 16 sockets HPE Integrity Superdome X from Hewlett Packard Enterprise from USA, but so that to be the highest "availability" on x86 architecture, i advice you to buy the 16 sockets HPE NONSTOP X SYSTEMS from Hewlett Packard Enterprise from USA, and read about it here: https://www.hpe.com/hpe-external-resources/4aa4-2000-2999/enw/4aa4-2988?resourceTitle=Engineered+for+the+highest+availability+with+HPE+Integrity+NonStop+family+of+systems+brochure&download=true And here is more of my thoughts about the history of HP NonStop on x86: More of my philosophy about HP and about the Tandem team and more of my thoughts.. I invite you to read the following interesting article so that to notice how HP was smart by also acquiring Tandem Computers, Inc. with there "NonStop" systems and by learning from the Tandem team that has also Extended HP NonStop to x86 Server Platform, you can read about it in my below writing and you can read about Tandem Computers here: https://en.wikipedia.org/wiki/Tandem_Computers , so notice that Tandem Computers, Inc. was the dominant manufacturer of fault-tolerant computer systems for ATM networks, banks, stock exchanges, telephone switching centers, and other similar commercial transaction processing applications requiring maximum uptime and zero data loss: https://www.zdnet.com/article/tandem-returns-to-its-hp-roots/ More of my philosophy about HP "NonStop" to x86 Server Platform fault-tolerant computer systems and more.. Now HP to Extend HP NonStop to x86 Server Platform HP announced in 2013 plans to extend its mission-critical HP NonStop technology to x86 server architecture, providing the 24/7 availability required in an always-on, globally connected world, and increasing customer choice. Read the following to notice it: https://www8.hp.com/us/en/hp-news/press-release.html?id=1519347#.YHSXT-hKiM8 And today HP provides HP NonStop to x86 Server Platform, and here is an example, read here: https://www.hpe.com/ca/en/pdfViewer.html?docId=4aa5-7443&parentPage=/ca/en/products/servers/mission-critical-servers/integrity-nonstop-systems&resourceTitle=HPE+NonStop+X+NS7+%E2%80%93+Redefining+continuous+availability+and+scalability+for+x86+data+sheet So i think programming the HP NonStop for x86 is now compatible with x86 programming. More of my philosophy about the 16 sockets HPE Integrity Superdome X from Hewlett Packard Enterprise from USA and more of my thoughts.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, so i think that parallel programming with memory on Intel's CXL will be different than parallel programming the many memory channels and on many sockets, so i think so that to scale much more the memory channels on many sockets and be compatible, i advice you to for example buy the 16 sockets HPE Integrity Superdome X from Hewlett Packard Enterprise from USA here: https://cdn.cnetcontent.com/3b/dc/3bdcd896-f2b4-48e4-bbf6-a75234db25da.pdf And i am sure that my below Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well will work correctly on the 16 sockets HPE Superdome X. More of my philosophy about the future of system memory and more of thoughts.. Here is the future of system memory of how to scale like with many more memory channels: THE FUTURE OF SYSTEM MEMORY IS MOSTLY CXL Read more here: https://www.nextplatform.com/2022/07/05/the-future-of-system-memory-is-mostly-cxl/ So i think the way to parallel programming in the standard Intel's CXL will look like parallel programming with many memory channels as i am doing it below with my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well. More of my philosophy about x86 CPUs and about cache prefetching and more of my thoughts.. I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, and today i will talk about the how to prefetch data into the caches on x86 microprocessors: So here my following delphi and freepascal x86 inline assembler procedures that prefetch data into the caches: So for 32 bit Delphi and Freepascal compilers, here is how to prefetch data into the level 1 cache and notice that, in delphi and freepascal compilers, when we pass the first parameter of the procedure with a register convention, it will be passed on CPU register eax of the x86 microprocessor: procedure Prefetch(p : pointer); register; asm prefetchT1 byte ptr [eax] end; For 64 bit Delphi and Freepascal compilers, here is how to prefetch data into the level 1 cache and notice that, in delphi and freepascal compilers, when we pass the first parameter of the procedure with a register convention, it will be passed on CPU |
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